1:4 LVDS Fanout Buffer, NECL and TTL Inputs

SKU:

$ 1,811.25

Item	Description
88000102-4	Cable, triple voltage, with modular plugs, Length in ft.
88000103-4	Cable, triple voltage, with modular plug and pig tail leads, Length in ft.

Product Description
Diagrams
Applications
Specifications
Documents

Applications:

LVDS Fanout Buffer
Converting NECL or Sinewave Signals to LVDS
Converting TTL Signals to LVDS
High Speed Digital Communications Systems Testing
Satellite Telemetry/Ground Station System Integration

Features:

f_MAX > 1.25GHz for NECL, > 300 MHz for TTL input
Single-ended or Differential NECL Input with Internal 50 Ω/V_TT Input Termination also accepts Sinewave or AC-coupled Signals
Separate TTL input (1 V minimum) Logically ORed with NECL Inputs
4 Pairs of Complementary 50 Ω LVDS Outputs
500 ps Typical Output Rise & Fall Times
SMA Connectors for NECL Inputs
BNC Connector for TTL Input
SMA Output Connectors
Self-contained 1.3 x 2.9 x 5-in. unit includes ±8.5 V/1.8 A AC/DC Adapter

Description

The PRL-424NLV is a 1:4 fanout, complementary output, LVDS line driver. It is intended for converting NECL signals, AC-coupled sine waves, or TTL signals into multiple LVDS signals for driving long lines. The PRL-424LV high speed fanout line driver facilitates testing of high speed digital communications circuits and distribution of satellite signals.

The PRL-424NLV has two logically ORed input circuits:

For the NECL input a switch selects either single-ended or differential inputs, as shown in Fig. 1. In the differential input mode, both inputs D and D are terminated internally into 50 Ω/V_TT, where V_TT is –2 V for NECL. In the differential input mode, therefore, either one or both inputs can accept AC coupled signals as well⁽¹⁾. In the single-ended input mode, signals should be connected to the D input only. The D input is switched internally to V_BB, nominally -1.3 V for NECL, and termination resistor R_T for the D input channel is changed to 62 Ω. The connectors for the NECL input are SMA.
The TTL input has a 50 Ω input termination with a minimum 1 V triggering threshold. The TTL input connector is BNC. When using the TTL input the NECL input selector switch should be in the Down position to prevent spurious triggering.

The four pairs of complementary outputs are 50 Ω back-terminated and are designed for driving floating 100 Ω loads, normally the configuration used in LVDS input circuits. The output swing is typically 600 mV with a common mode voltage of 1.2 V. All output connectors are SMA.

The PRL-424NLV is supplied with a ±8.5 V/1.8 A AC/DC adapter and housed in a 1.3 x 2.9 x 5-in. extruded aluminum enclosure. Available accessories include voltage distribution modules and brackets for mounting multiple units.

(1) A related model, the PRL-424LV, has a "universal differential" input (floating 100 Ω termination) that will accept LVDS, RS-422, NECL and LVPECL, so long as the NECL and LVPECL signals are differential and have internal pull-down resistors.

Fig. PRL-424NLV Block Diagram

(0° C ≤ T_A ≤ 35° C)*

SYMBOL	PARAMETER	Min	Typ	Max	UNIT	Comment
R_IN	Input Resistance	49.5	50	50.5	Ω
V_TT	D Input Termination Voltage (fixed)	-2.2	-2.0	-1.8	V
V_T1	D Input Termination Voltage	-1.17	-1.30	-1.43	V	Switch Down
V_T2	D Input Termination Voltage	-2.20	-2.00	-1.80	V	Switch Up
V_IL	Input Lo Voltage	-1.95	-1.60	-1.48	V
V_IH	Input Hi Voltage	-1.13	-0.90	-0.81	V
V_OL	Output Low Level		0.9		V
V_OH	Output High Level		1.5		V
V_IL	Input Lo Voltage	-1.95	-1.60	-1.48	V
I_DC1	DC Input Current, +8.5 V		130	140	mA
I_DC2	DC Input Current, -8.5 V		-470	-480	mA
V_DC	DC Input Voltage	±7.5	±8.5	±12	V
V_AC1	AC/DC Adapter Input Voltage, 120	103	115	127	V
V_AC1	AC/DC Adapter Input Voltage, 220	206	220	254	V
t_PLH	Propagation Delay to output ↑		2.7		ns
t_PHL	Propagation Delay to output ↓		2.7		ns
t_r/t_f1	Rise/Fall Times (10%-90%)¹		500	650	ps	@ 200 MHz
t_r/t_f2	Rise/Fall Times (10%-90%)¹		250		ps	@ 1.25 GHz
t_SKEW	Skew between any 2 outputs		200	550	ps
f_MAX1	Max Clock Frequency, SMA Input²	1.25	1.35		GHz
f_MAX2	Max Clock Frequency, TTL Input		300		MHz
	Size	1.3 x 2.9 x 5.0			in.
	Weight	8			Oz
	Shipping Weight	4			lbs

Notes:
(1) Rise and Fall times are measured with ground-referenced 50 Ω loads.
(2) f_max is measured using the PRL-174ANT Clock Driver outputs as the driver and the PRL-425N with SMA input connectors as the receiver. The outputs of the PRL-425N are then measured. f_max for the TTL input is currently limited by the lack of TTL drivers faster than 300 MHz.

PDF Datasheet