2 x 1:8 Logic Translator/Fanout Buffer, LVDS Inputs, TTL Outputs

Applications:

• Translating LVDS signals to TTL signals
• TTL/CMOS Clock/Trigger Distribution
• Synchronous Clocking/ Triggering of Dalsa X64 Xcelera-HS PX8 and similar framegrabbers
• High Speed Digital Communications System Testing

Features:

• f_MAX > 80 MHz, 90 MHz typical
• Drives 100 ft of cable @ 50 MHz
• 1.8 ns Typical Output Rise & Fall Times
• 2.5 V into 50 Ω Typical
• 2 x 100 Ω Triax LVDS Inputs
• 2 x Eight In-phase 50 Ω TTL SMA Outputs
• DC Coupled I/Os
• Valid signal LED indicators
• Self-contained 1U, 19” rackmount enclosure

Description

The PRL-4520 is  2 x 1:8 logic level translator and fanout buffer with two LVDS Triax inputs and sixteen 50 Ω TTL/SMA outputs. It is designed for translation and distribution of high-speed clock and trigger signal to multiple loads via long lines, especially the synchronous clocking/triggering of Dalsa X64 Xcelera-HS PX8 and similar framegrabbers. The 50 Ω back-terminated outputs can drive long lines with or without 50 Ω load terminations. With 50 Ω load terminations, however, all outputs of the PRL-4520 can drive 100 ft of 50 Ω cables at clock rates greater than 50 MHz.

Each input channel of the PRL-4520 has a differential 100 Ω LVDS Triax input and eight 50 Ω back terminated TTL SMA outputs, which typically deliver 2.5 V into 50 Ω or 5.0 V into Hi-Z loads.  A valid signal LED indicator is provided for each channel.  All I/Os are DC coupled. An equivalent circuit of the PRL-4250 LVDS input is shown in Fig. 1, and the internal signal fanout and distribution block diagram is shown in Fig. 2. 

The PRL-4250 is housed in a standard 1U, 19” rackmount enclosure.  External 8V/12V, 2A DC power is required. The PRL-4520 may be with ordered with a custom silkscreen, which case the model would be identified as PRL-4520-C00x, where each configuration would have a unique suffix, but all PRL-4520 units will have the same form factor and electrical function.