12 GHz Programmable 2-Phase Frequency Divider (f/8-f/128)

SKU:

$ 1,713.50

Quantity

Item	Description
88000102-4	Cable, triple voltage, with modular plugs, Length in ft.
88000103-4	Cable, triple voltage, with modular plug and pig tail leads, Length in ft.

Product Description
Diagrams
Applications
Specifications
Documents

Applications:

System Clock Simulation
Low Jitter NECL Clock Source
SONET Clock Generator
Laser Pump Synchronization
Scope triggering
PRBS/BERT synchronization
Optimizing outputs from frequency synthesizers
Testing high-speed serial/SERDES links (GB Ethernet, eSATA, PCIe, HT, etc)
An Essential Lab Tool for Working with NECL Circuits

Features:

12 GHz typical maximum External Clock Input frequency
f/8 to f/128 with independent 2Φ outputs
Common Divide by 8 pre-scalar for both Φ1 and Φ2
Φ1 output = (f/8)/(1, 2, 4 or 8), for max. ratio of 64
Φ2 output = (f/8)/(2, 4, 8 or 16), for max. ratio of 128
Both Φ1 and Φ2 have two pairs of complementary NECL square wave outputs
Single-ended AC Coupled Input with internal 50 Ω termination
5 ps typical Edge Jitter
40 ps typical skew between f/n & f/n NECL outputs
Complementary DC coupled NECL Outputs drive 50 Ω loads terminated to -2 V, AC-coupled or floating 50 Ω loads
SMA I/O Connectors
Ready-to-Use 1.3 x 2.9 x 2.9-in. Module includes a ±8.5V AC/DC Adapter

Description

The PRL-257-8 is an AC-coupled input, manually programmable, two phase frequency divider with two sets of complementary NECL outputs. It is capable of running at input frequencies in excess of 12 GHz.

It has a common divide-by-8 pre-scalar front end followed by two banks of independent manually programmable dividers, Φ1and Φ2. The f/8 pre-scalar output is further divided by 1, 2, 4, or 8 for the Φ1 bank via D0 and D1 of a two-bit DIP switch, providing a maximum ratio of 64. It is divided by 2, 4, 8 or 16 for the Φ2 bank via D2 and D3 of a second two-bit DIP switch, providing a maximum ratio of 128. All outputs are synchronous with the input frequency and are square waves (50% duty cycle) suitable for driving long lines terminated into 50 Ω/-2 V or AC-coupled 50 Ω loads.

The PRL-257-8 is ideal for applications where a high frequency divider or pre-scalar is needed for triggering or down-sampling. The two phases of output enable applications requiring two different ratios from a common reference frequency, and the 1:2 fanout feature enables system synchronization and monitoring/triggering applications from a single reference clock source. Applications for the PRL-257-8 include data acquisition, test, measurement, R&D, and system integration.

The unit includes an AC adapter for ready-to-use convenience on the bench or in a system. All I/O connectors are SMA. The extruded aluminum housing is suitable for mounting with the optional brackets.

Fig. 2: PRL-257-8 Block Diagram

Sample Applications and Test Results

The PRL-257-8 was reviewed by a well-respected member of the Signal Integrity mailing list:

". . . the device has a [specified] bandwidth up to 12GHz, and my measurements show that its actual bandwidth goes out to 14GHz. I thought that was very good margin. But what really impressed me was the jitter performance. I fed in a clock source with 170fs one sigma RJ, and the clock divider puts out a divided down clock with 770fs one sigma RJ. That is surprisingly good for a small device with such high bandwidth. Usually you would expect this kind of performance from a device weighing 40 lb and takes up a whole lot of bench top space, but this clock divider is small enough to fit in your pocket."

The full review is available at the si-list archives.

Scope shots from his testing are below:

Fig. 3: PRL-257-8 Output Waveform, 14 GHz input clock divided by 64

Fig. 4: PRL-257-8 Jitter Performance*, 10.3125 GHz clock divided by 8

Fig. 5: PRL-257-8 Jitter Performance*, 10.3125 GHz clock divided by 64

Fig. 6: PRL-257-8 Jitter Performance*, 2.125 GHz clock divided by 8

* These test results, though typical, are not guaranteed performance specifications.

SPECIFICATIONS (0° C ≤ T_A ≤ 35° C)*

Symbol	Parameter	PRL-257-8			Unit	Comments
Symbol	Parameter	Min	Typ	Max	Unit	Comments
R_IN	Input Resistance		50		Ω	AC Coupled
C_C	Coupling Capacitor	0.08	0.10	0.12	µf	Input TC=50 µs
V_INmin	Minimum p-p Input Amplitude	500 350 100	400 250 50		mV mV mV	Sine Wave@ F_{MIN In I} Square Wave, tr <2ns Square Wave, tr <500ps
V_INmax	Maximum p-p Input Amplitude		2.00	1.25	V	Sine or Square Wave
V_OL	Output Lo Voltage @ 100 MHz	-1.95	-1.60	-1.48	V	Output terminated to 50 Ω/-2V
V_OH	Output Hi Voltage @ 100 MHz	-1.13	-0.90	-0.81	V	Output terminated to 50 Ω/-2V
I_DC1	DC Input Current, +8.5 V		+80	+100	mA
I_DC2	DC Input Current, -8.5 V		-285	-300	mA
V_DC	DC Input Voltage	±7.5	±8.5	±12	V
V_AC	AC/DC Adapter Input Voltage	103	115	127	V
t_PLH	Propagation Delay to Φ1 output ↑		2500		ps
t_PHL	Propagation Delay to Φ1 output ↓		2500		ps
t_r/t_f	Rise/Fall Times (20%-80%)		200	250	ps	Note (1)
t_SKEW1	Skew↔ Φ1 or Φ2 outputs		40	120	ps
t_SKEW2	Skew↔ Φ1 and Φ2 outputs		40	120	ps	D0/D1=10, D2/D3=00
	Jitter, p-p		5	10	ps	Note (2)
F_{MIN In I}	Minimum Input frequency	120	100		MHz	Sine wave input
F_{MIN In II}	Minimum Input frequency	150	100		KHz	Square wave input
F_{MAX In I}	Maximum Input frequency	10.0	12.0	12.5	GHz
F_{MAX Out1}	Maximum Output frequency, Φ1	1.25	1.50	1.56	GHz	Φ1 outputs
F_{MAX Out2}	Maximum Output frequency, Φ2	0.625	0.750	0.780	GHz	Φ2 outputs
	Size	1.3 x 2.9 x 2.9			in.
	Weight, excl. AC adapter	10			Oz.
	Shipping weight, incl. AC adapter	3			lb.

* All measurements are made with outputs terminated into 50 Ω/V_TT.

Notes:

(1)

The output rise and fall times are measured with with all inputs terminated into 50 Ω/V_TT. For best performance all outputs should be terminated into 50 Ω/V_TT or else AC- coupled into 50 Ω loads. If a single output is used, its complement must be terminated; otherwise output waveform distortion will occur. If one pair of complementary outputs is used, the other complementary pair may remain unterminated. Use the PRL-550 Series, four channel ECL/PECL/LVPECL Terminators, for the 50 Ω/V_TT termination and for connection of ECL/PECL/LVPECL signals to 50 Ω input oscilloscopes. The PRL-ACT-50, Dual Channel AC-Coupled 50 Ω Terminator, may also be used to provide the 50 Ω/V_TT termination. If preservation of DC levels is not required, then the PRL-SC-104, 0.1 µf DC block or the PRL-ACX-12dB, 12 dB AC-coupled attenuator, may be used to connect the NECL/PECL/LVPECL outputs to 50 Ω input instruments.

(2)

Jitter specification limited by PRL internal test equipment. Independent testing shows typical jitter performance of < 1 ps one-sigma RJ.

PDF Datasheet