Small Signal Freq. Divider (f/2, f/4), NECL Outputs

SKU:

$ 1,581.25

Item	Description
88000102-4	Cable, triple voltage, with modular plugs, Length in ft.
88000103-4	Cable, triple voltage, with modular plug and pig tail leads, Length in ft.

Product Description
Diagrams
Applications
Specifications
Documents

Applications:

GHz Frequency Division in Device Test and Systems Integration
High speed Clock signal Generation for SONET applications
An Essential Lab Tool for Working with GHz ECL Circuits

Features:

2 GHz Toggle Frequency
Single-ended or Differential Inputs
Complementary NECL Outputs drive 50 Ω Loads terminated to -2 V
DC Coupled I/Os
SMA I/O Connectors
Ready-to-Use 1.3 x 2.9 x 3.9-in.Module includes a ±8.5 V AC/DC Adapter

Description

The PRL-255CN is a dual-channel ÷2 and ÷4 frequency divider with DC-coupled, 50 Ω comparator inputs, and complementary NECL outputs. The maximum frequency of operation is greater than 2 GHz, and the minimum input signal required is 10 mV_PP at 300 MHz. It is ideally suited for dividing mV sinewave signals or small pulses from laser oscillator photodiodes.

The two channels can be cascaded to provide a ÷8 function. The PRL-255CN is an essential lab tool for device test and systems integration in wireless and digital communications applications.

The comparator input threshold voltage for the PRL-255CN can be set to +50 mV, 0 V or -50 mV using the common three-position switch provided. It can also be varied independently in each channel by applying a DC bias voltage to one of the two inputs. In this case, a feed through decoupling capacitor of 0.1 µf, such as the PRL-FTC-104, is recommended for preventing false triggering or oscillation if the bias voltage contains varying components, such as noise. Input common mode range is -2.5 V to +4 V. To prevent oscillation in a non-driven channel when the preset threshold is set to 0 V, connect an output to an input so that the two inputs are not at the same voltage.

The PRL-255CN is housed in a 1.3 x 2.9 x 3.9-in. enclosure and supplied with a ±8.5 V/1.8 A AC/DC Adapter.

PRL-255CN Block Diagram

SPECIFICATIONS (0° C ≤ T_A ≤ 35° C)*

Symbol	Parameter	PRL-255CN			Unit	Comments
Symbol	Parameter	Min	Typ	Max	Unit	Comments
R_IN	Input Resistance	49.5	50.0	50.5	Ω
V_TH+	Preset Positive Threshold Voltage	+40	+50	+60	mV
V_TH-	Preset Negative Threshold Voltage	-60	-50	-40	mV
V_{TH 0}	Preset Zero Threshold Voltage	-5	0	+5	mV
V_IN Min 1	Minimum Input Voltage p-p	10	5		mV	0 < f < 300 MHz
V_IN Min 2	Minimum Input Voltage p-p	400	200		mV	300 MHz < f < 2.5 GHz
I_DC	DC Input Current		+35 -310	+55 -350	mA mA
V_DC	DC Input Voltage	±7.5	±8.5	±12	V
V_AC	AC/DC Adapter Input Voltage	103	115	127	V
t_PLH(÷2)	Propagation Delay to output ↑		1.8	2.2	ns
t_PHL(÷2)	Propagation Delay to output ↓		1.8	2.2	ns
t_PLH(÷4)	Propagation Delay to output ↑		2.0	2.5	ns
t_PHL(÷4)	Propagation Delay to output ↓		2.0	2.5	ns
t_r/t_f	Rise/Fall Times (20%-80%)		400	600	ps	Note (1)
t_SKEW	Skew between Q& Q outputs		50	150	ps
F_MAX	Max clock frequency	2.0	2.5		GHz	Note (3)
V_CMR	Common Mode Range	-2.5		+4	V
	Size	1.3 x 2.9 x 3.9			in.
	Shipping weight, incl. AC adapter	4			lb.

* All measurements are made with outputs terminated into 50 Ω/V_TT.

Notes:

The output rise and fall times are measured with with all inputs terminated into 50 Ω/V_TT. For best performance all outputs should be terminated into 50 Ω/V_TT or else AC- coupled into 50 Ω loads. If a single output is used, its complement must be terminated; otherwise output waveform distortion will occur. If one pair of complementary outputs is used, the other complementary pair may remain unterminated. Use the PRL-550 Series, four channel ECL/PECL/LVPECL Terminators, for the 50 Ω/V_TT termination and forconnection of ECL/PECL/LVPECL signals to 50 Ω input oscilloscopes. The PRL-ACT-50, Dual Channel AC-Coupled 50 Ω Terminator, may also be used to provide the 50 Ω/V_TTtermination. If preservation of DC levels is not required, then the PRL-SC-104, 0.1 µf DC block or the PRL-ACX-12dB, 12 dB AC-coupled attenuator, may be used to connect the NECL/PECL/LVPECL outputs to 50 Ω input instruments.

(2). These parameters are not supplied by the device manufacturer and are, therefore, not guaranteed.

(3). f_MAX is measured by AC coupling a sine wave to the ÷2 CLK input using the differential input mode (switch up). The ÷2 and the ÷4 dividers are cascaded, and the ÷8 outputs are then measured. The f_MAX measurement is then repeated by clocking the ÷4 CLK input with the sine wave.

PDF Datasheet

Small Signal Freq. Divider (f/2, f/4), NECL Outputs

Applications:

Features:

Description

SPECIFICATIONS (0° C ≤ TA ≤ 35° C)*

* All measurements are made with outputs terminated into 50 Ω/VTT.

Notes:

(2). These parameters are not supplied by the device manufacturer and are, therefore, not guaranteed.

(3). fMAX is measured by AC coupling a sine wave to the ÷2 CLK input using the differential input mode (switch up). The ÷2 and the ÷4 dividers are cascaded, and the ÷8 outputs are then measured. The fMAX measurement is then repeated by clocking the ÷4 CLK input with the sine wave.

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SPECIFICATIONS (0° C ≤ T_A ≤ 35° C)*

* All measurements are made with outputs terminated into 50 Ω/V_TT.

(3). f_MAX is measured by AC coupling a sine wave to the ÷2 CLK input using the differential input mode (switch up). The ÷2 and the ÷4 dividers are cascaded, and the ÷8 outputs are then measured. The f_MAX measurement is then repeated by clocking the ÷4 CLK input with the sine wave.