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DescriptionThe PRL-4540 is an 4 channel logic level translator system with four single-ended, 50 Ohm TTL inputs on BNC connectors and four differential TTL output pairs on a mass-terminated D38999/20FC35SN connector. It is designed for translation of high-speed clock and trigger signals. The TTL inputs have a fixed at 50 Ω impedance, but require only 1.5 V to trigger. A set of internal toggle switch can reduce this further to 1.0 V. The differential TTL outputs are designed to drive twisted pair cabling into either 100 Ω/124 Ω floating loads or 50 Ω loads to Ground. The outputs of the PRL-4540 can toggle at clock rates greater than 250 MHz, typical. All I/Os are DC coupled. The PRL-4540 is equivalent to 2 units of the PRL-420TD, 2 Channel TTL to Differential TTL Translator, integrated into a 1U chassis with an internal, auto-switching 120 VAC/240 VAC power supply, and an internal 88001641-2-C00x breakout cable with mass-terminated output connector. The PRL-4540 may be with ordered custom pinout on the 20FC35SN connector and/or with a custom silkscreen, which case the model would be identified as PRL-4540-C00x, where each configuration has a unique suffix, but all PRL-4540 units will have the same form factor and electrical function. Use matching breakout cable 88001642-6-C00x, 26FC35PN to 8 x SMA-M, for testing. |
Fig. 2: PRL-4540 Block Diagram
Fig. 3: 26FC35PN Pin Mating Face
| Pinout C002 | ||
| Pin | Signal | Coax Connection |
| 1 | CH1(+) | Sub cable 1A signal |
| 2 | CH1(-) | Sub cable 1B signal |
| 3 | Sub cable 1 shield | |
| 4 | CH2(+) | Sub cable 2A signal |
| 5 | CH2(-) | Sub cable 2B signal |
| 6 | Sub cable 2 shield | |
| 7 | CH3(+) | Sub cable 3A signal |
| 8 | CH3(-) | Sub cable 3B signal |
| 9 | Sub cable 3 shield | |
| 10 | CH4(+) | Sub cable 4A signal |
| 11 | CH4(-) | Sub cable 4B signal |
| 12 | Sub cable 4 shield | |
(0° C ≤ TA ≤ 35° C)*
| Symbol | Parameter | PRL-4540 | Unit | Comments | ||
|---|---|---|---|---|---|---|
| Min | Typ | Max | ||||
| RIN | Input Resistance | 49.5 | 50.0 | 50.5 | Ω | |
| ROUT | Differential Output Resistance | 99 | 100 | 101 | Ω | |
| VTOSH | Input Threshold Voltage (high) | 1.4 | 1.5 | 1.6 | V | Internal switches Up (default) |
| VTOSL | Input Threshold Voltage (low) | 0.9 | 1.0 | 1.1 | V | Internal switches Down |
| VIL | TTL input Low Level | -0.5 | 0.0 | 0.5 | V | |
| VIH | TTL input Low Level | 1.8 | 2.0 | 5.0 | V | |
| VOL | Differential TTL Output Low Level | -0.1 | 0.0 | 0.5 | V | 50 Ω load |
| VOH | DifferentialTTL Output High Level | 2.0 | 2.5 | 2.6 | V | 50 Ω load |
| IDC1 | DC Input Current, +8.5 V | 340 | 360 | mA | Each internal unit | |
| IDC2 | DC Input Current, -8.5 V | -360 | -340 | mA | Each internal unit | |
| VDC | DC Input Voltage | ±7.5 | ±8.5 | ±12 | V | Internal units |
| VAC | AC Input Voltage | 100 | 264 | V | 50/60 Hz Auto-Switching | |
| tPLH | Propagation Delay to output ↑ | 7 | ns | |||
| tPHL | Propagation Delay to output ↓ | 7 | ns | |||
| tr/tf(1) | Rise/Fall Times (10%-90%) | 1.0 | 1.4 | ns | ||
| tSKEW | Skew between any 2 outputs | 150 | 400 | ps | ||
| fMAX | Max Clock Frequency | 200 | 250 | MHz | ||
| Size (W x H x D) | 18.95 x 1.75 x 13.10 | in. | 11.78" D from rack face | |||
| Weight | 5.5 | lb. | ||||
*Unless otherwise specified, dynamic measurements are made with all outputs terminated into 50 Ω.
